A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having capacitors and its manufacture method.
B) Description of the Related Art
Generally, a high frequency analog integrated circuit used in a mobile communication field or the like requires passive elements such as resistors, capacitors and inductors in addition to active elements (transistors and the like) operable at high speed, because of the characteristics of signals to be processed. In order to improve an operation speed and reduce a consumption power, it is necessary to reduce parasitic capacitance and resistance. In order to reduce parasitic capacitance and resistance, a capacitor of a metal-insulator-metal (MIM) structure is used more than a capacitor of a metal-oxide-semiconductor (MOS) structure.
FIG. 7 is a cross sectional view of a semiconductor device having wirings formed by a damascene method and capacitors of a MIM structure. A capacitor of the MIM structure having a structure similar to that shown in FIG. 7 is disclosed in “A high Reliability Metal Insulator Metal Capacitor for 0.18 μm Copper Technology” by M. Armacost, et. al., IEDM2000, pp. 157-160. In the following, a manufacture method for the semiconductor device shown in FIG. 7 will be described.
An etching stopper film 101 of SiN and an interlayer insulating film 102 of SiO2 are formed on an interlayer insulating film 100. A wiring trench is formed through these two films and a copper wiring 103 is embedded in this wiring trench. On the interlayer insulating film 102, an etching stopper film 106 of SiN is formed, having a copper diffusion prevention and etching stopper function. A SiO2 film 112 is thinly formed on the etching stopper film 106. This SiO2 film 112 is not essential. A recess 110 is formed extending from the upper surface of the SiO2 film 112 to the upper surface of the interlayer insulating film 100.
A TiN film as a lower electrode 115A, an SiO2 film as a capacitor dielectric film 116A, a TiN film as an upper electrode 117A and an SiN film as an upper insulating film 118A are sequentially deposited on the whole surface of the substrate. These four layers are deposited also on the inner surface of the recess 110. The four layers from the lower side TiN film to the SiN film are patterned in a shape of the lower electrode 115A. In this case, a step formed in the recess 110 is used as an alignment mark. Since the upper surface of the interlayer insulating film 102 is flat, the position of the lower level wiring 103 cannot be detected after the TiN film is formed on the interlayer insulating film 102. The recess 110 is therefore formed to use it as the alignment mark.
Next, the SiO2 film, upper level TiN film and SiN film are patterned in a shape of the upper electrode 117A. A capacitor 119 is constituted of the lower electrode 115A of TiN, capacitor dielectric film 116A of SiO2, and upper electrode 117A of TiN. The TiN film 115B, SiO2 film 116B, upper TiN film 117B and SiN film 118B are also left on the inner surface of the recess 110.
When the lower electrode 115A is formed, an alignment mark is formed at a position different from the lower electrode 115A. By using this alignment mark, alignment is performed when the SiO2 film, upper TiN film and SiN film are patterned in the shape of the upper electrode 117A. Depending upon the an allowable range of position alignment precision of the upper and lower electrodes, the step in the recess 110 can be used as the alignment mark when pattering into the shape of the upper electrode 117A.
An interlayer insulating film 120 is formed covering the capacitor 119, and the surface of the interlayer insulating film 120 is planarized. Via holes 122A, 122B and 122C are formed through the interlayer insulating film 120. The via hole 122A passes beside the upper electrode 117A and exposes the upper surface of the lower electrode 115A. The via hole 122B passes through the upper insulating film 118A and exposes the upper surface of the upper electrode 117A. The via hole 122C passes through the SiO2 film 112 and etching stopper film 106 and exposes the upper surface of the lower level wiring 103.
After the inner surfaces of these via holes 122A, 122B and 122C are covered with a barrier metal film, plugs made of tungsten (W) are embedded in the via holes. Wirings 125A, 125B and 125C of aluminum (Al) or the like are formed on the interlayer insulating film 120. The wirings 125A, 125B and 125C are connected to the plugs embedded in the via holes 122A, 122B and 122C, respectively.
With the above-described manufacture method, it is necessary to conduct photolithography once at each of the process of forming the recess 110, the process of patterning the lower electrode 115A and the process of patterning the upper electrode 117A. Namely, three photolithography processes are newly added as compared to the case in which the capacitor 119 is not formed.
With reference to FIGS. 8A to 8D, description will be made on a method for manufacturing a capacitor of the MIM structure disclosed in JP-A-2003-51501.
As shown in FIG. 8A, a wiring 152 is embedded in a wiring recess formed in an interlayer insulating film 150, and a lower electrode 151 is embedded in a capacitor recess. An etching stopper film 155 is formed on the interlayer insulating film 150, lower electrode 151 and wiring 152. An interlayer insulating film 156 is formed on the etching stopper film. A capacitor recess 156A is formed through the interlayer insulting film 156. The recess 156A partially overlaps the lower electrode 151 as viewed in plan.
A barrier metal film is formed on the whole substrate surface, and a conductive film is deposited on the barrier metal film. Chemical mechanical polishing (CMP) is performed until the upper surface of the interlayer insulating film 156 is exposed. An upper electrode 158 is therefore formed as shown in FIG. 8B, being made of the conductive film left in the recess 156A.
As shown in FIG. 8C, an etching stopper film 160 is formed on the interlayer insulating film 156 and upper electrode 158, and an interlayer insulating film 161 is formed on the etching stopper film 160.
As shown in FIG. 8D, a recess 161B is formed through the interlayer insulating film 161 and etching stopper film 160, and a via hole 156B is formed extending from the bottom of the recess 161B to the upper surface of the wiring 152. As viewed in plan, the recess 161B overlaps the upper electrode 158 and low-level wiring 152. The upper electrode 158 is exposed on a partial bottom of the recess 161B, and the upper surface of the wiring 152 is exposed on the bottom of the via hole 156B.
The inner surfaces of the recess 161B and via hole 156B are covered with a barrier metal film, and the recess 161B and via hole 156B are filled with a conductive member 163. A capacitor is therefore formed by the lower electrode 151 and upper electrode 158 and the etching stopper 155 disposed between the two electrodes. The upper electrode 158 is connected via the conductive member 163 to the wiring 152 formed in the same layer as that of the lower electrode 151.